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FEATURES Factory Set Gain AD8079A: Gain = +2.0 (Also +1.0 & -1.0) AD8079B: Gain = +2.2 (Also +1 & -1.2) Gain of 2.2 Compensates for System Gain Loss Minimizes External Components Tight Control of Gain and Gain Matching (0.1%) Optimum Dual Pinout Simplifies PCB Layout Low Crosstalk of -70 dB @ 5 MHz Excellent Video Specifications (RL = 150 ) Gain Flatness 0.1 dB to 50 MHz 0.01% Differential Gain Error 0.02 Differential Phase Error Low Power of 50 mW/Amplifier (5 mA) High Speed and Fast Settling 260 MHz, -3 dB Bandwidth 750 V/ s Slew Rate (2 V Step), 800 V/ s (4 V Step) 40 ns Settling Time to 0.1% (2 V Step) Low Distortion of -65 dBc THD, fC = 5 MHz High Output Drive of Over 70 mA Drives Up to 8 Back-Terminated 75 Loads (4 Loads/ Side) While Maintaining Good Differential Gain/ Phase Performance (0.01%/0.17 ) High ESD Tolerance (5 kV) Available in Small 8-Pin SOIC APPLICATIONS Differential A-to-D Driver Video Line Driver Differential Line Driver Professional Cameras Video Switchers Special Effects RF Receivers PRODUCT DESCRIPTION
Dual 260 MHz Gain = +2.0 & +2.2 Buffer AD8079
FUNCTIONAL BLOCK DIAGRAM 8-Pin Plastic SOIC
+IN1 1 GND GND +IN2 2 8 7 OUT1 +VS -VS OUT2
AD8079
3 4 6 5
cables and transformers. Its low distortion and fast settling are ideal for buffering high speed dual or differential A-to-D converters. The AD8079 features a unique transimpedance linearization circuitry. This allows it to drive video loads with excellent differential gain and phase performance of 0.01% and 0.02 on only 50 mW of power per amplifier. It features gain flatness of 0.1 dB to 50 MHz. This makes the AD8079 ideal for professional video electronics such as cameras and video switchers. The AD8079 offers low power of 5 mA/amplifier (VS = 5 V) and can run on a single +12 V power supply while delivering over 70 mA of load current. All of this is offered in a small 8-pin SOIC package. These features make this amplifier ideal for portable and battery powered applications where size and power are critical. The outstanding bandwidth of 260 MHz along with 800 V/s of slew rate make the AD8079 useful in many general purpose high speed applications where dual power supplies of 3 V to 6 V are required. The AD8079 is available in the industrial temperature range of -40C to +85C.
1 0 RL = 100 VIN = 50mV rms SIDE 1 -2
NORMALIZED FLATNESS - dB NORMALIZED FREQUENCY RESPONSE - dB
The AD8079 is a dual, low power, high speed buffer designed to operate on 5 V supplies. The AD8079's pinout offers excellent input and output isolation compared to the traditional dual amplifier pin configuration. With two ac ground pins separating both the inputs and outputs, the AD8079 achieves very low crosstalk of less than -70 dB at 5 MHz. Additionally, the AD8079 contains gain setting resistors factory set at G = +2.0 (A grade) or Gain = +2.2 (B grade) allowing circuit configurations with minimal external components. The B grade gain of +2.2 compensates for gain loss through a system by providing a single-point trim. Using active laser trimming of these resistors, the AD8079 guarantees tight control of gain and channel-channel gain matching. With its performance and configuration, the AD8079 is well suited for driving differential REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
SIDE 2
-1
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 1M 10M 100M FREQUENCY - Hz 1G
50 50
-3 -4 -5 SIDE 2 SIDE 1 -6 -7 -8 -9
Figure 1. Frequency Response and Flatness
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 1996
AD8079-SPECIFICATIONS (@ T = +25 C, V =
A S
5 V, RL = 100
Min
, unless otherwise noted)
AD8079A/AD8079B Typ Max 260 50 100 750 800 40 2.5 -65 -70 2.0 2.0 0.01 0.01 0.02 0.07 10 10 20 3.0 15 20 6.0 10 2.002/2.202 2.005/2.205 Units MHz MHz MHz V/s V/s ns ns dBc dB nV/Hz pA/Hz % % Degree Degree mV mV V/C A A V/V V/V % % M pF V V mA mA 6.0 11.5 V mA dB dB A/V
Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth Bandwidth for 0.1 dB Flatness Large Signal Bandwidth Slew Rate Settling Time to 0.1% Rise & Fall Time NOISE/HARMONIC PERFORMANCE Total Harmonic Distortion Crosstalk, Output to Output Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Offset Voltage, RTO
Conditions VIN = 50 mV rms VIN = 50 mV rms VIN = 1 V rms VO = 2 V Step VO = 4 V Step VO = 2 V Step VO = 2 V Step fC = 5 MHz, VO = 2 V p-p f = 5 MHz f = 10 kHz f = 10 kHz, +In NTSC, R L = 150 NTSC, RL = 75 NTSC, R L = 150 RL = 75
TMIN-TMAX Offset Drift, RTO +Input Bias Current Gain Gain Matching INPUT CHARACTERISTICS +Input Resistance +Input Capacitance OUTPUT CHARACTERISTICS Output Voltage Swing Output Current1 Short Circuit Current1 POWER SUPPLY Operating Range Quiescent Current/Both Amplifiers Power Supply Rejection Ratio, RTO +Input Current TMIN-TMAX No Load RL = 150 Channel-to-Channel, No Load Channel-to-Channel, RL = 150 +Input +Input R L = 150 RL = 75 2.7 1.998/2.198 1.995/2.195
2.0/2.2 2.0/2.2 0.1 0.5 10 1.5 3.1 2.8 70 110
85 3.0 TMIN-TMAX +VS = +4 V to +6 V, -VS = -5 V -VS = - 4 V to -6 V, +VS = +5 V TMIN-TMAX 49 40
10.0 69 50 0.1
0.5
NOTES 1 Output current is limited by the maximum power dissipation in the package. See the power derating curves. Specifications subject to change without notice.
-2-
REV. A
AD8079
ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V Internal Power Dissipation2 Small Outline Package (R) . . . . . . . . . . . . . . . . . . 0.9 Watts Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range . . . . . . . . . . . . . -65C to +125C Operating Temperature Range (A Grade) . . . -40C to +85C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300C
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 8-Pin SOIC Package: JA = 160C/Watt
The maximum power that can be safely dissipated by the AD8079 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately +150C. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of +175C for an extended period can result in device failure. While the AD8079 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (+150C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves.
2.0 TJ = +150C
MAXIMUM POWER DISSIPATION - Watts
1.5
1.0
9
8-PIN SOIC PACKAGE
0.5
0 -50 -40 -30 -20 -10
0
10 20
30 40
50 60 70
80 90
AMBIENT TEMPERATURE - C
Figure 2. Plot of Maximum Power Dissipation vs. Temperature
ORDERING GUIDE
Model AD8079AR AD8079AR-REEL AD8079AR-REEL7 AD8079BR AD8079BR-REEL AD8079BR-REEL7
Gain G = +2.0 G = +2.0 G = +2.0 G = +2.2 G = +2.2 G = +2.2
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 8-Pin Plastic SOIC REEL SOIC REEL 7 SOIC 8-Pin Plastic SOIC REEL SOIC REEL 7 SOIC
Package Option SO-8 SO-8 SO-8 SO-8 SO-8 SO-8
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8079 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
-3-
AD8079
1 0 +5V 10F 0.1F 2 7
NORMALIZED FLATNESS - dB NORMALIZED FREQUENCY RESPONSE - dB
RL = 100 VIN = 50mV rms
SIDE 2 SIDE 1
-1 -2
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 1M 10M 100M FREQUENCY - Hz 1G
50 50
-3 -4 -5 SIDE 2 SIDE 1 -6 -7 -8 -9
AD8079
VIN PULSE GENERATOR TR/TF = 250ps 50 1 6
8 0.1F 10F RL = 100
-5V
Figure 3. Test Circuit
Figure 6. Frequency Response and Flatness
-50
100mV STEP
-60
RL = 100
SIDE 1
DISTORTION - dBc
-70 2ND HARMONIC -80 3RD HARMONIC -90
-100
SIDE 2
20mV
5ns
-110 10k
100k
1M FREQUENCY - Hz
10M
100M
Figure 4. 100 mV Step Response
Figure 7. Distortion vs. Frequency, RL = 100
-60
1V STEP SIDE 1
RL = 1k VOUT = 2Vp-p -70
DISTORTION - dBc
-80 2ND HARMONIC -90 3RD HARMONIC -100
SIDE 2
-110
200mV
5ns
-120 10k 100k 1M FREQUENCY - Hz 10M 100M
Figure 5. 1 V Step Response
Figure 8. Distortion vs. Frequency, RL = 1 k
-4-
REV. A
AD8079
-10 -20 -30
CROSSTALK - dB
3
VS = 5V
INPUT LEVEL - dBV
-3 -6 -9 -12 -15 -18 -21 V IN = 125mV rms V IN = 0.25V rms V IN = 0.5V rms
-3 -6 -9 -12 -15 -18 -21 V IN = 62.5mV rms -24 100M -27 500M
-40 -50 -60 -70 -80 -90
-24
-100 -110 100k 0.1M 1M 10M FREQUENCY - Hz 100M 200M
-27 1M
10M FREQUENCY - Hz
Figure 9. Crosstalk (Output-to-Output) vs. Frequency
Figure 12. Large Signal Frequency Response
0.02
5 NTSC 2 BACK TERMINATED LOADS (75) 4 3 1 BACK TERMINATED LOAD (150) 1 2 3 4 5 6 IRE 7 8 9 10 11 0.1%/DIV 2 1 0 -1 -2 1 BACK TERMINATED LOAD (150) -3 -4 -5 1 2 3 4 5 6 IRE 7 8 9 10 11 0 20 40 60 TIME - ns 80 100 120 2V STEP RC = 100 RL = 150
DIFF GAIN - %
0.01 0.00 -0.01 -0.02
NORMALIZED OUTPUT LEVEL - dBV
VIN = 2V p-p RL = 100
0
V IN = 1.0V rms
VS = 5V RL = 100
3 0
9
DIFF PHASE - Degrees
0.08 0.06 NTSC 0.04 0.02 0.00 2 BACK TERMINATED LOADS (75)
Figure 10. Differential Gain and Differential Phase (per Amplifier)
Figure 13. Short-Term Settling Time
RL = 100 SIDE 1
2V STEP RL = 100
ERROR, (0.05%/DIV)
SIDE 2
OUTPUT
INPUT
5ns
NOTES: SIDE 1: VIN = 0V; 8mV/div RTO SIDE 2: 1V STEP RTO; 400mV/div
400mV
2s
Figure 11. Pulse Crosstalk, Worst Case, 1 V Step
Figure 14. Long-Term Settling Time
REV. A
-5-
AD8079
3.4 3.3 3.2 OUTPUT SWING - Volts 3.1 3.0 2.9 2.8 2.7 2.6 2.5 -55 9.0 -55 +VOUT |-VOUT| RL = 150 11.5
TOTAL SUPPLY CURRENT - mA
VS = 5V
11.0
10.5 VS = 5V 10.0
9.5
-35
-15
5 25 45 65 85 JUNCTION TEMPERATURE - C
105
125
-35
-15 5 25 45 65 85 JUNCTION TEMPERATURE - C
105
125
Figure 15. Output Swing vs. Temperature
Figure 18. Total Supply Current vs. Temperature
7 6
120 115
SHORT CIRCUIT CURRENT - mA
INPUT BIAS CURRENT - A
5 4 3 +IN 2 1 0 -1 -55
110 105 100 95 90 85 80 75 |SINK ISC| SOURCE ISC
-35
-15
5
25
45
65
85
105
125
JUNCTION TEMPERATURE - C
70 -55
-35
-15
5 25 45 65 85 JUNCTION TEMPERATURE - C
105
125
Figure 16. Input Bias Current vs. Temperature
Figure 19. Short Circuit Current vs. Temperature
8 DEVICE #1
100
100
INPUT OFFSET VOLTAGE RTO - mV
Hz
6
2 DEVICE #2 0 DEVICE #3
10 NONINVERTING CURRENT VS = 5V
10
-2
VOLTAGE NOISE VS = 5V
-4 -6 -55
1 10 100 1k FREQUENCY - Hz 10k 1 100k
-35
-15 5 25 45 65 85 JUNCTION TEMPERATURE - C
105
125
Figure 17. Input Offset Voltage vs. Temperature
Figure 20. Noise vs. Frequency
-6-
REV. A
NOISE CURRENT - pA/
4
NOISE VOLTAGE, RTI - nV/
Hz
AD8079
THEORY OF OPERATION
100 VS = 5.0V POWER = 0dBm (223.6mV rms) RbT = 0 RbT = 50
10
1
0.1
0.01 10k 100k 1M 10M FREQUENCY - Hz 100M 1G
The AD8079, a dual current feedback amplifier, is internally configured for a gain of either +2 (AD8079A) or +2.2 (AD8079B). The internal gain-setting resistors effectively eliminate any parasitic capacitance associated with the inverting input pin, accounting for the AD8079's excellent gain flatness response. The carefully chosen pinout greatly reduces the crosstalk between each amplifier. Up to four back-terminated 75 video loads can be driven by each amplifier, with a typical differential gain and phase performance of 0.01%/0.17, respectively. The AD8079B, with a gain of +2.2, can be employed as a single gain-trimming element in a video signal chain. Finally, the AD8079A/B used in conjunction with our AD8116 crosspoint matrix, provides a complete turn-key solution to video distribution.
Printed Circuit Board Layout Considerations
RESISTANCE -
Figure 21. Output Resistance vs. Frequency
-44.0 -46.5 -49.0 -51.5 2V SPAN PSRR - dB -54.0 -56.5 -59.0 -61.5 -64.0 -66.5 -69.0 -55 +PSRR CURVES ARE FOR WORST CASE CONDITION WHERE ONE SUPPLY IS VARIED WHILE THE OTHER IS HELD CONSTANT. -PSRR
As to be expected for a wideband amplifier, PC board parasitics can affect the overall closed-loop performance. If a ground plane is to be used on the same side of the board as the signal traces, a space (5 mm min) should be left around the signal lines to minimize coupling. Line lengths on the order of less than 5 mm are recommended. If long runs of coaxial cable are being driven, dispersion and loss must be considered.
Power Supply Bypassing
9
-35
-15
5 25 45 65 85 JUNCTION TEMPERATURE - C
105
125
Adequate power supply bypassing can be critical when optimizing the performance of a high frequency circuit. Inductance in the power supply leads can form resonant circuits that produce peaking in the amplifier's response. In addition, if large current transients must be delivered to the load, then bypass capacitors (typically greater than 1 F) will be required to provide the best settling time and lowest distortion. A parallel combination of 4.7 F and 0.1 F is recommended. Some brands of electrolytic capacitors will require a small series damping resistor 4.7 for optimum results.
DC Errors and Noise
Figure 22. PSRR vs. Temperature
0 VIN = 200mV -4 -14 -24
-PSRR
-34 -44 -54 -64 -74 -84 30k
+PSRR
100k
1M 10M FREQUENCY - Hz
100M
500M
There are three major noise and offset terms to consider in a current feedback amplifier. For offset errors refer to the equation below. For noise error the terms are root-sum-squared to give a net output error. In the circuit below (Figure 24) they are input offset (VIO) which appears at the output multiplied by the noise gain of the circuit (1 + R F/RI), noninverting input current (IBN x RN) also multiplied by the noise gain, and the inverting input current, which when divided between RF and RI and subsequently multiplied by the noise gain always appears at the output as IBN x RF. The input voltage noise of the AD8079 is a low 2 nV/Hz. At low gains though the inverting input current noise times RF is the dominant noise source. Careful layout and device matching contribute to better offset and drift specifications for the AD8079 compared to many other current feedback amplifiers. The typical performance curves in conjunction with the equations below can be used to predict the performance of the AD8079 in any application.
V OUT =V IO x 1+
RF RF I BN x RN x 1 + I BI x RF RI RI
PSRR - dB
Figure 23. PSRR vs. Frequency
where: RF = RI = 750 for AD8079A RF = 750 , RI = 625 for AD8079B
REV. A
-7-
AD8079
RF (INTERNAL) RI (INTERNAL) I BI RSERIES VOUT CL
2 7 0.1F 75 CABLE VOUT #2 75 +VS 75 75 CABLE VOUT #1 4.7F 75
RN
I BN
1/2 AD8079
1
75 8
Figure 24. Output Offset Voltage
Driving Capacitive Loads
V IN
6
0.1F
75 CABLE
4.7F -VS
The AD8079 was designed primarily to drive nonreactive loads. If driving loads with a capacitive component is desired, best frequency response is obtained by the addition of a small series output resistance (RSERIES). The graph in Figure 25 shows the optimum value for RSERIES vs. capacitive load. It is worth noting that the frequency response of the circuit when driving large capacitive loads will be dominated by the passive roll-off of RSERIES and CL.
40
75
4
1/2 AD8079
75 5
75 CABLE VOUT #3 75 75 CABLE VOUT #4 75
3
75
30
Figure 26. Video Line Driver
RSERIES -
Single-Ended to Differential Driver Using an AD8079
20
10
0
0
5
10 C L - pF
15
20
25
Figure 25. Recommended RSERIES vs. Capacitive Load
Operation as a Video Line Driver
The two halves of an AD8079 can be configured to create a single-ended to differential high speed driver with a -3 dB bandwidth in excess of 110 MHz as shown in Figure 27. Although the individual op amps are each current feedback with internal feedback resistors, the overall architecture yields a circuit with attributes normally associated with voltage feedback amplifiers, while offering the speed advantages inherent in current feedback amplifiers. In addition, the gain of the circuit can be changed by varying a single resistor, RF, which is often not possible in a dual op amp differential driver.
CC = 1.5pF RF 750
The AD8079 has been designed to offer outstanding performance as a video line driver. The important specifications of differential gain (0.01%) and differential phase (0.02) meet the most exacting HDTV demands for driving one video load with each amplifier. The AD8079 also drives four back terminated loads (two each), as shown in Figure 26, with equally impressive performance (0.01%, 0.07). Another important consideration is isolation between loads in a multiple load application. The AD8079 has more than 40 dB of isolation at 5 MHz when driving two 75 back terminated loads.
RG 750 VIN
OP AMP #1 1/2 AD8079
50 OUTPUT #1
1/2 AD8079 OP AMP #2
50 OUTPUT #2
Figure 27. Differential Line Driver
-8-
REV. A
AD8079
The current feedback nature of the op amps, in addition to enabling the wide bandwidth, provides an output drive of more than 3 V p-p into a 20 load for each output at 20 MHz. On the other hand, the voltage feedback nature provides symmetrical high impedance inputs and allows the use of reactive components in the feedback network. The circuit consists of the two op amps each configured as a unity gain follower by the 750 feedback resistors between each op amp's output and inverting input. The output of each op amp has a 750 resistor to the inverting input of the other op amp. Thus, each output drives the other op amp through a unity gain inverter configuration. By connecting the two amplifiers as cross-coupled inverters, their outputs are free to be equal and opposite, assuring zero-output common-mode voltage. With this circuit configuration, the common-mode signal of the outputs is reduced. If one output moves slightly higher, the negative input to the other op amp drives its output to go slightly lower and thus preserves the symmetry of the complementary outputs which reduces the common-mode signal. The resulting architecture offers several advantages. First, the gain can be changed by changing a single resistor. Changing either RF or RG will change the gain as in an inverting op amp circuit. For most types of differential circuits, more than one resistor must be changed to change gain and still maintain good CMR. Reactive elements can be used in the feedback network. This is in contrast to current feedback amplifiers that restrict the use of reactive elements in the feedback. The circuit described requires about 1.3 pF of capacitance in shunt across RF in order to optimize peaking and realize a -3 dB bandwidth of more than 110 MHz. The peaking exhibited by the circuit is very sensitive to the value of this capacitor. Parasitics in the board layout on the order of tenths of picofarads will influence the frequency response and the value required for the feedback capacitor, so a good layout is essential. The shunt capacitor type selection is also critical. Good microwave type chip capacitors with high Q were found to yield best performance.
6 4 2 0 CC = 1.3pF VIN = 10dBm
OUTPUT - dB
-2 -4 -6 -8 OUT+
-10 -12 -14 0.1M 1M 10M FREQUENCY - Hz
OUT-
100M
1G
Figure 28. Differential Driver Frequency Response
Layout Considerations
The specified high speed performance of the AD8079 requires careful attention to board layout and component selection. Proper RF design techniques and low parasitic component selection are mandatory. The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance ground path. The ground plane should be removed from the area near the input pins to reduce stray capacitance. Chip capacitors should be used for supply bypassing (see Figure 29). One end should be connected to the ground plane and the other within 1/8 in. of each power pin. An additional large (4.7 F-10 F) tantalum electrolytic capacitor should be connected in parallel, but not necessarily so close, to supply current for fast, large-signal changes at the output. Stripline design techniques should be used for long signal traces (greater than about 1 in.). These should be designed with a characteristic impedance of 50 or 75 and be properly terminated at each end.
9
REV. A
-9-
AD8079
+VS IN RT 50 OUT
-VS
Inverting Configuration
+VS C1 0.1F C2 0.1F -VS C3 10F C4 10F
Supply Bypassing
+VS 50 OUT IN RT -VS
Figure 30. Board Layout (Silkscreen)
*SEE TABLE I
Noninverting Configuration (G = +2)
TRIM 200 IN RT
AD8079B
OUT
Optional Gain Trim (G = +2 +2.2)
TIE INPUT PINS TOGETHER TO MINIMIZE PEAKING IN RT -VS
Figure 31. Board Layout (Component Layer)
+VS
OUT
Noninverting Configuration (G = +1)
Figure 29. Inverting and Noninverting Configurations
Table I. Recommended Component Values
Component RT (Nominal) () Small Signal BW (MHz) 0.1 dB Flatness (MHz)
-1 53.6 220 50
+1 49.9 750 100
+2/+2.2 49.9 260 50
Figure 32. Board Layout (Solder Side; Looking Through the Board)
-10-
REV. A
AD8079
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC (SO-8)
0.1968 (5.00) 0.1890 (4.80)
8 1 5 4
0.1574 (4.00) 0.1497 (3.80)
0.2440 (6.20) 0.2284 (5.80)
PIN 1 0.0688 (1.75) 0.0098 (0.25) 0.0040 (0.10) 8 0 0.0500 (1.27) 0.0160 (0.41) 0.0532 (1.35) 0.0196 (0.50) 0.0099 (0.25) x 45
SEATING PLANE
0.0500 0.0192 (0.49) (1.27) 0.0138 (0.35) BSC
0.0098 (0.25) 0.0075 (0.19)
9
REV. A
-11-
-12-
C2185a-xx-11/96
PRINTED IN U.S.A.

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